Circuitry for converting analog signals into corresponding, equivalent digital signals has a multiplicity of uses in present day instrumentation and telemetry equipment. One prior art analog-to-digital (A-to-D) converter known as the "dual ramp" type is comprised of an analog portion and a digital or logic portion. The analog portion generally includes a controllable voltage switch, an integrator and a comparator. The input terminal of the integrator is connected through a resistor to the output terminal of the voltage switch, and the output terminal of the integrator is connected to the comparator. The logic portion generally includes a clock, a gate, a counter, a bistable multivibrator (flip-flop), a storing circuit and a processing circuit. The gate has a first input terminal connected to the output terminal of the clock and a second input terminal connected to the output terminal of the comparator. The counter is connected to the output terminal of the gate. One output terminal of the counter is connected through the flip-flop to the control terminal of the voltage switch, and other output terminals of the counter are connected through latch and multiplexer circuits to a binary-coded-decimal (BCD) display or other digital utilization and processing circuitry.
In operation, the voltage switch connects an unknown input voltage at a first of its input terminals to the integrator which stores a charge in response to the input voltage while the clock drives the counter. The input voltage causes a first ramp voltage at the output of the integrator. After a predetermined time period, a given count in the counter triggers the flip-flop which causes the voltage switch to disconnect the input voltage and connect a reference voltage, of opposite polarity as compared with the input voltage, to the input terminal of the integrator. At the instant when the voltage switch changes state, the output voltage of the integrator is at a peak which is proportional to the magnitude of the input voltage. The reference voltage causes the magnitude of the output voltage of the integrator to decrease from its peak value toward a zero or reference level at a constant slope to form a second ramp. The counter is reset simultaneously with the start of the second ramp. Since the peak of the second ramp is proportional to the magnitude of the input voltage and the slope of the second ramp is constant, the time period for the second ramp to reach zero is proportional to the magnitude of the input voltage. The comparator is triggered by the output voltage of the integrator reaching the reference level and turns off the gate which disconnects the clock from the counter. As a result the count, in the form of a binary output signal existing in the counter, is proportional to the magnitude of the input voltage. After the binary output is stored in the latch circuit, another conversion cycle begins during which the binary output may be processed and the storage cleared.
One of the several advantages of the dual ramp system is that the binary output signal is independent of changes in the integrator capacitor, the integrator resistor, and the clock rate because all three are common to the first and second ramps. Hence, the long term variations of these parameters cancel out. Moreover, long term changes in the comparator threshold voltage is balanced out by the dual ramp system. Hence, the dual ramp, A-to-D converter system, has distinct advantages as compared to some other prior art A-to-D systems for applications in which the magnitude of an unknown voltage is required to be precisely measured and provided in digital form. One such application relates to a digital volt meter (DVM) which provides a decimal output display of the magnitude of a direct current voltage applied to the input terminals thereof.
Prior art embodiments of the analog portion of the dual ramp configuration requires at least four integrated circuits and a plurality of discrete active and passive components having critical values. These configurations are not suitable for being provided in the form of one monolithic integrated circuit. For instance prior art analog portions, capable of responding to input voltages of either polarity, require two large field effect transistors (FETs) for performing voltage switching. Such low resistance FET devices take up a large amount of chip area. Moreover, these FETs have undesirably slow switching times because of high capacitances associated therewith. Furthermore, other circuitry of the analog portion is best provided in bipolar form. Since inexpensive processes for providing FET devices and bipolar devices in the same chip are not known, prior art configurations requiring both kinds of devices are not desirable for being provided in one chip.
Another problem with prior art dual ramp circuit configurations relates to providing an analog portion which can respond to input voltages of different polarities. Most prior art systems are set up for an input voltage of given polarity. Thus the reference voltage must be switched in polarity, and the logic must be reversed if the polarity of the input signal is changed. Conventional operational amplifiers and integrators suitable for providing this function require a dual power supply providing three voltage potentials which increases the cost, complexity, size and weight of the sytem.
Still another problem with some prior art configurations occurs when zero input voltage is applied to the converter. As the input voltage approaches zero, the amount of current fed to the integrator also approaches zero and the intial ramp slope approaches zero. As the ramp slope decreases, noise is more likely to trigger the circuitry and the circuit is likely to lock up in a static state thereby causing false outputs. Furthermore, some of the prior art systems require precision resistors and capacitors which are not suitable for being provided in monolithic form by an inexpensive process. Hence, the prior art discrete analog circuit configurations cannot be readily adapted to take advantage of the increased reliability, smaller size, lower weight, reduced cost, and lower power dissipation inherent in monolithic structures.